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L****cas
Shared or separate SPI buses for peripherals in a PCB?
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Apr 11.2019, 10:57:23
I have four SPI-controlled chips which I want to control from Zynq-7020 via an FMC LPC connector. Each chip/device requires an SCLK, MISO, MOSI and CS line.
I'd like to give each device their own separate SPI bus, but for my given application, I don't have enough clock capable (CC) pins on the FMC LPC connector to give each device their own SPI SCLK. I do have enough pins to give each device separate MISO, MOSI and CS lines. There are a few options on what I could do, and I am wondering what the advantages/disadvantages of each would be:
1) Every device shares a single SPI bus (Separate CS lines, but shared SCLK, MISO, MOSI)
2) Shared SCLK, but separate MISO, MOSI, and CS lines for each device
3) Separate SPI buses, driving SCLKs through LA pins instead of CC pins on the FMC LPC interface. (I am not sure if my FPGA would like that I am driving a clock from a non-CC pin)
My target device is a PCB, what implications would each of the three options have on my design, and what would be the best option?
I'd like to give each device their own separate SPI bus, but for my given application, I don't have enough clock capable (CC) pins on the FMC LPC connector to give each device their own SPI SCLK. I do have enough pins to give each device separate MISO, MOSI and CS lines. There are a few options on what I could do, and I am wondering what the advantages/disadvantages of each would be:
1) Every device shares a single SPI bus (Separate CS lines, but shared SCLK, MISO, MOSI)
2) Shared SCLK, but separate MISO, MOSI, and CS lines for each device
3) Separate SPI buses, driving SCLKs through LA pins instead of CC pins on the FMC LPC interface. (I am not sure if my FPGA would like that I am driving a clock from a non-CC pin)
My target device is a PCB, what implications would each of the three options have on my design, and what would be the best option?
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M****ong
Apr 11.2019, 13:58:21
1 - If your SPI clock is slow, less than 10 MHz, you can use a GPIO to generate the clock. At this speed, you have enough timing margin, you don't need a dedicated clock output. The SPI "Clock" can be generated using a counter.
2 - Having a dedicated SPI clock is usually better for EMC. I have a seen a few cases where a slow-ish free-running clock would cause noise and EMC problems.
3 - Having seperate SPI links mean you can communicate in parallel with these devices. It can be helpful in some applications...
2 - Having a dedicated SPI clock is usually better for EMC. I have a seen a few cases where a slow-ish free-running clock would cause noise and EMC problems.
3 - Having seperate SPI links mean you can communicate in parallel with these devices. It can be helpful in some applications...
