We're having some trouble with yield on a consumer product that incorporates one of ST's accelerometer chips. We're failing up to 40% of our assembled boards during testing because the accelerometer readings are out of spec. The test methodology is basically looking for offset along each of the X, Y, and Z axes... and our error bands are actually larger than what the OEM recommends. If we used their guidelines, we'd have an even lower yield.
These failures a specific to the accel chip in that we can take a failing board, replace the accel by hand, and it'll be perfect. If we take an accel chip from a failing board and reflow it onto a previously working PCB, the failure moves with the bad part.
We have two hypotheses: 1) some kind of SMT issue is causing stress on the accel package which causes these offsets. 2) Ham-handed depanelization at the CM. Our panels use mouse bites (not fully routed) and individual boards are snapped out using a jig. Perhaps the snapping process causes too much shock and damages some of the MEMS chips.
Maybe 3) would be a bad reel of parts from ST, but I find that really hard to believe.
Does anyone have experience with this kind of problem? How would you go about finding the root cause.
- Comments(1)
A****min
Dec 12.2019, 18:59:23
Take a panel and pull it through your entire process as you would do otherwise.
Take another panel and test the circuits without depanneling.