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PCB Stackup Planning

This Application Note details tried and proven techniques for planning high speed Multilayer PCB Stackup configurations. There will probably be as many teories as there are designers out there, but this is a “keep it simple” article to give you a start.

BASIC
There are two major applications areas, RF/analog and Digital.
The major differences between these two areas are the ability of the PCB involved to tolerate signal losses and the complexity of the PCB.

RF/Analog applications are characterized by the need for low dielectric losses, low leakage, a need for a low and uniform dielectric constant (Dk)  followed by a low layer count. Since this type of PCB “tends” to be small,  cost of the dielectric material has less effect on overall product cost than on other components. As a result, using more exotic and expensive materials to meet performance goals is acceptable.

For this class of PCB, choosing a material based on it’s Dk characteristics and losses usually dominates over other considerations.

Digital applications are characterized by high layer counts, a large numbers of drilled, plated holes, and they can have buried, blind and very small via holes.

The processing costs associated with registering,  laminating, bonding many layers, drilling and plating ease,  usually dominate the choice of materials. Absolute Dk value of the insulating material is important, but less important than processing costs and dimensional stability.

As a result, woven glass reinforced materials are nearly always required. The choice of resin system used with the glass reinforcement is made based on keeping Z-axis expansion within acceptable limits. Also CAF materials (Conductive Anodic Filament) shall be considered for very complex PCBs. The thicker the PCB, the higher the Tg must be to produce a reliable PCB. Digital applications are nearly always subjected to pricing pressures, so material choices must be made to just achieve performance requirements without adding extra cost.

Planning the multilayer PCB stackup configuration is one of the most important aspects in achieving the best possible performance of a circuit. A poorly designed substrate, with inappropriately selected materials, can degrade the electrical performance of signal transmission increasing emissions and crosstalk and can also make the PCB more susceptible to external noise. These issues can cause intermittent operation due to timing glitches and interference dramatically reducing the products performance and long term reliability.

In contrast, a properly built PCB substrate can effectively reduce electromagnetic emissions, crosstalk and improve the signal integrity providing a low inductance power distribution network. And, looking from a fabrication point of view, can also improve manufacturability of the board.

Suppressing the noise at the source rather than trying to elevate the problems once the board has been built makes sense. Having the project completed ‘Right First Time’ on time and to budget means that you cut costs by reducing the design cycle, have a shorter time to market and an extended product life cycle.

Boards containing copper planes allow signals to be routed in either microstrip or stripline controlled impedance transmission line configurations creating much less radiation than the indiscriminate traces on a two layer board. The signals are tightly coupled to the planes (either ground or power) reducing crosstalk and improving signal integrity.

Planes, in multilayer PCB’s, provide significant reduction in radiated emission over two layer PCBs. As a rule of thumb, a four layer board will produce 15 dB less radiation than a two layer board.  With ref to impedance requirements, changes in physical parameters will affect impedance as follow:

When selecting a multilayer stackup we should consider the following:

-     A signal layer should always be adjacent to a plane. This limits the number of signal layers embedded between planes to two and top and bottom (outer) layers to one signal.

-     Signal layers should be tightly coupled (<250um) to their adjacent planes

-     A power plane (as well as a ground) can be used for the return path of the signal.

-     Determine the return path of the signals (which plane will be used). Fast rise time signals take the path of least inductance which is normally the closest plane.

-     Cost (the boss's most important design parameter).

-     Symmetrical- balanced build. Consider an imaginary line in the middle of the board. This will devide the board in a upper Into upper and lower half.

-     The copper layers in the top half of the board should match with the the bottom half of the board.

-     The layer to layer separation in the top half of the board should match with the bottom half of the board.

-     The material used in upper and lower half of the board should be the same to avoid warpage.

-     The stack-up for hybrid boards should be reviewed by manufacturer on design to design basis.

-     Chose of material shall also be done with considerations to number of heating prosesses, soldering- and possible repair- rounds.

-     Use IPC4101C and the under groups to define the material to use in your stackup.

-     Specific material shall only be defined when there are electrical considerations that is locking your design to a specific material.

Soldermask – Affects on Impedance
Since PCB’s are normally covered in Soldermask then the affects of the conformal coating should be considered when calculating impedance. Generally, soldermask will reduce the impedance by 2 to 3 ohms on thin traces. As the trace thickness increases the soldermask has less affect.

Figure 1 illustrates the effect of soldermask coating on microstrip impedance. This example is of commonly used liquid photoimageable soldermask having a thickness of 12.7um and a Dielectric Constant of 3.3. The soldermask drops the microstrip characteristic impedance by ca 2 ohms and the differential impedance by 3.5 ohms. So, if you don’t consider soldermask then the calculation could be out by as much as 3 to 4%.

Dielectric Materials
The most popular Dielectric material is FR4 and may be in the form of core or prepreg (preimpregnated) material.

The core material is thin dielectric (cured fibreglass epoxy resin) with copper foil bonded to both sides. For instance: Isola's FR406 materials - include 127, 200, 241, 356, 457, 534, 711, 890, 1000, 1200, 1500 and 2360 um cores. The copper thickness is typically &frac12; to 2 oz (17 to 70 um).

The prepreg material is thin sheets of fibreglass impregnated with uncured epoxy resin which hardens when heated and pressed during the PCB fabrication process. Isola’s FR406 materials – include 43, 58, 100 and 180 um prepregs that may be combined to achieve the desired prepreg thickness.

The most common stackup called the ‘Foil Method’ is to have prepreg with copper foils bonded to the outside on the outer most layers (top and bottom) then core alternating with prepreg throughout the substrate. An alternate stackup is called the ‘Caped Method’ which is the opposite of the Foil Method and was used by old-school military contractors.

Let’s take a look at some common multilayer configurations.

4 Layer Stackup
A typical four layer board stackup is shown below. The Characteristic and Differential Impedances of the substrate are calculated using the ICD Stackup Planner.

It is common to see four layer boards stacked evenly. That is, four evenly spaced layers with the planes in the centre. Although, this certainly makes the board symmetrical it doesn’t help the EMC.

Also, another common mistake is to have the planes closely coupled in the centre with large dielectrics between the signal layers and planes. This certainly creates good interplane capacitance but again doesn’t help with signal integrity, crosstalk or EMC – which is why we opt for a four layer PCB over a two layer.

To improve the EMC performance of a four layer board, it is best to space the signal layers as close to the planes as possible (< 250um), and use a large core (~ 100um) between the power and ground plane keeping the overall thickness of the substrate  to ~1.6mm. The close trace to plane coupling will decrease the crosstalk between traces and allow us to maintain the impedance at an acceptable value.

A good range of impedance (Zo) is from 50 to 60 ohms. Keep in mind that lower impedance will increase the dI/dt and dramatically increase the current drawn (not good for the PDN) and higher impedance will emit more EMI and also make the design more susceptible to outside interference.

6 Layer Stackup
A six layer board is basically a four layer board with two extra signal layers added between the planes. This improves the EMI dramatically as it provides two buried layers for high-speed signals and two surface layers for routing low speed signals.

The signal layers should be placed very close to there adjacent planes and the desired board thickness (62 MIL) made up by the use of a thicker centre core. It is always a compromise between trace impedance, trace width and prepreg/core thickness and it is best to use a stackup calculator to provide quick ‘what if’ analysis of the possibilities.

The ICD Stackup Planner calculates characteristic impedance plus edge coupled and broadside coupled differential impedance. The latter for embedded dual stripline layers only. Differential pairs are becoming common place in high speed design reducing noise by using differential mode signalling.

8 Layer Stackup
To improve EMC performance, add two more planes to the six layer stackup. It is not recommended to have more then two adjacent signal layers between the planes as this creates impedance discontinuities (~20 ohms difference in impedance of signal layers) and increases crosstalk between these signal layers.

In the case below, two plane layers are added to the centre of the substrate. This allows tight coupling between the centre planes and isolates each signal plane reducing coupling hence crosstalk dramatically. This configuration is commonly used for high speed signals of DDR2 and DDR3 designs where crosstalk due to tight routing is an issue. If you are risk aversive – then this is the stackup to use.

10 Layer Stackup
A ten layer board should be used when six routing layers and four planes are required and EMC is of concern.

Figure 5 above demonstrates a typical 10 layer stackup. This stackup is ideal because of the tight coupling of the signal and return planes, the shielding of the high speed signal layers, the existence of multiple ground planes, as well as a tightly coupled power/ground plane pair in the center of the board. High speed signals normally would be routed on the signal layers buried between planes (layers 3-4 and 7-8 in this case).

However, care should be taken to route these signal orthogonally, with respect to each other, to avoid coupling (crosstalk) between adjacent layers.

12 Layer Stackup

Twelve layers is close to the largest number of layers that usually can be conveniently fabricated in a 1.6mm thick board.  But we see more an more 14 to 16 layer boards fabricated as a 1.6mm thick board as well, but the numbers of fabricators capable of producing them are limited to those that can produce HDI boards. And those who can produce HDI boards are increasing.

High layer count boards (ten plus) require thin dielectrics (typically 127um or less on a 1.6mm thick board) and therefore they automatically have tight coupling between layers. When properly stacked and routed they can meet all of our high speed requirements and will have excellent EMC performance and signal integrity. The above twelve layer stackup provides shielding on six of the internal layers.

14 Layer Stackup
The fourteen layer stackup below is used when eight routing (signal) layers are required plus special shield of critical nets is required. Layers 6 and 9 provide isolation for sensitive signals while layers 3 & 4 and 11 & 12 provide shielding for high speed signals.

16 Layer Stackup
A sixteen layer PCB provides ten layers of routing and is normally used for extremely dense designs. Generally, you see 16 layer PCB’s where the routing technology used in the EDA application doesn’t have ability to route the design to completion. “If it won’t route - just keep adding layers”. Although this is a common saying it is not good practice.

If a board won’t route to completion then there may be a number of reasons. Poor placement is often the course. Open routing channels, reduce the number of crossovers in the rats nets, place vias on a 25 MIL grid to allow through routing and basically help the router as much as possible.

There is really no limit to the number of layers that can be fabricated in a multilayer PCB (please check the capabilities of your fabricator first). Of course, the board thickness increases as the layer count goes up to accommodate the minimum thickness of materials used. Also the aspect ratio (board thickness to smallest hole diameter) has to be considered. Generally this is 10:1 for boards thicker then 2.5mm. For example, a 5.0 mm thick substrate has a minimum hole size of 0.5mm.

Determining the Layer Count

The technology rules are based on the minimum pitch of the SMT components employed and are basically the largest trace, clearance and via allowable whilst minimising PCB fabrication costs. Technology of 100/100 um (trace/clearance) and Vias of 0.45/0.2mm (pad/hole) are generally required for complex high speed design incorporating ball grid arrays (BGA).

However, if you can use less demanding dimensions then this will reduce cost and improved fabrication yield.

Once these rules have been established, calculate the stackup required for the desired characteristic impedance (Zo) and the differential impedance (Zdiff) as per the component datasheets. Generally, 50 ohm Zo and 100 ohm Zdiff are used. Keep in mind that lower impedance will increase the dI/dt and dramatically increase the current drawn (not good for the PDN) and higher impedance will emit more EMI and also make the design more susceptible to outside interference. So, a good range of Zo is 50 – 60 ohms.

The total number of layers required for a given design is dependent on the complexity of the design. Factors include: the number of signal nets that must break out from a BGA; the number of power supplies required by the BGA’s; component density and package types.

We see more and more BGAs with pitch on 0.5 and 0.4mm. These components require micro vias directly in BGA pad to be able to route out on innerlayers. On outer layers, traces between BGA pads is not recommended. It will be nesessary to use stacked and staggered micro vias, maybe as deep as 4-5 micro vias stacked. This will take you from layer 1 down to layer 5. The deepest ones will be closest to the centre of the BGA, and the ones going from layer 1 to layer 2,  are maybe in use on BGA row number 2-3. On micro vias the Aspect ratio is below 1.


The  stackup shown in fig. 9 -16 and 9-16A  I have used 76um prepregs between layer 1-5 and layer 16-12 to be able to use micro vias between these layers. Between layer 5 and 12 (8 layers) I have placed a mechanically drilled buried via.

In this article I have used the In-Circuit Design Pty Ltd, Stackup Planner. It has been used by designers since 1996 and is simple and easy to use.  The generic stackups use default values for all variables that can be adjusted to achieve the desired Characteristic (Zo), Edge Coupled (Zdiff) and Broadside Coupled (Zdbs) Impedance. The Dielectric Constant (also called Relative Permittivity), Dielectric Thickness, Copper Thickness, Trace Width and Trace can be varied. The 2011 release also calculates trace current.