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label: printed-circuit-board,PCB trace,PCB design

Signal integrity and characteristic impedance

Signal-integrity problems can present some interesting issues as you try to stabilize the signals across your board. The IBIS (input/output-buffer-information-specification) model provides a simple approach to these problems. You can use an IBIS model to extract important variables for your signal-integrity calculations and PCB (printed-circuit-board) designs. The values that you extract from the IBIS model are integral parts of the signal-integrity-design calculations.

As you tackle transmission-line-matching issues in your system, you must understand the electrical impedances and characteristics of your ICs and PCB traces. Figure 1 shows a single-ended transmission line. With your transmission line, you can extract the transmitter’s output impedance, ZT, and the receiver’s input impedance, ZR, from the IC’s IBIS model. These IC specifications are sometimes unavailable in the IC manufacturer’s product data sheets, but you can pull all of these values from the IBIS model.

Four parameters define transmission lines: characteristic impedance, Z0; board propagation delay, D; line propagation delay tD; and trace length. Typically, the FR (flame-retardant)-4 board’s characteristic impedance ranges from 50 to 75Ω, and propagation delay ranges from 140 to 180 psec/in. The characteristic-impedance values depend on the actual transmission line’s material and physical dimensions (Reference 1). The line delay on your board equals the propagation delay times the length of your trace. With any board,   and tD=D×LENGTH, where CTR is the trace capacitance, LTR is the trace inductance, and eR is the PCB-material dielectric constant. For FR-4 boards, a reasonable strip-line propagation delay is 178 psec/in., with a characteristic impedance of 50Ω.

The transmitter specifications for a signal-integrity evaluation are output impedance, ZT. When determining the output impedance, the pin area in the IBIS model provides each pin’s resistive, inductive, and capacitive parasitic values. You then join the package capacitance with the respective buffer’s capacitive value, C_comp, to get a better picture.

A pin keyword relates to a package, as the component, manufacturer, and package above the pin keyword describe. You will find the package capacitance and inductance in the pin’s keyword table as it relates to the pin of interest. For instance, in the ads129x.ibs model (Reference 2), Listing 1, shows where you would look for the L_pin and C_pin values of signal GPIO4, pin 5E (64-pin PBGA package). The pin inductance and pin capacitance for this signal and package are 2.5339 nH and 0.28001 pF, respectively.

The second capacitance value of interest is the C_comp value under the model keyword. As you find the correct model in the IBIS model, you will find a list of C_comp values. Listing 2 shows an example of C_comp in the DIO_33 model (Reference 2).

In the statements in Listing 2, the | symbol indicates a comment. The text highlighted in yellow shows the active C_comp (Reference 3). From these lines in the listing, the PCB designer can choose among three values. During the PCB transmission-line design stage, the typical value of 3.072722 pF is an appropriate choice.

The IBIS model provides clues for PCB designers who perform board simulations before moving to the prototype stage. If you know where to look, the IBIS model provides the characteristic impedance and capacitance of all the pins. The next step in this evaluation is to determine the I/O resistance of each buffer. You will see this topic in a future column.